Memory device structure with protective element

ABSTRACT

A semiconductor device structure is provided. The structure includes a semiconductor substrate and a data storage element over the semiconductor substrate. The structure also includes an ion diffusion barrier element over the data storage element and a protective element extending along a sidewall of the ion diffusion barrier element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a Continuation application of U.S. patentapplication Ser. No. 17/000,537, filed on Aug. 24, 2020, which is aDivisional of U.S. application Ser. No. 15/821,901, filed on Nov. 24,2017, the entirety of which are incorporated by reference herein.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs. Each generation has smaller and more complexcircuits than the previous generation.

In the course of IC evolution, functional density (i.e., the number ofinterconnected devices per chip area) has generally increased whilegeometric size (i.e., the smallest component (or line) that can becreated using a fabrication process) has decreased. This scaling-downprocess generally provides benefits by increasing production efficiencyand lowering associated costs.

However, these advances have increased the complexity of processing andmanufacturing ICs. Since feature sizes continue to decrease, fabricationprocesses continue to become more difficult to perform. Therefore, it isa challenge to form reliable semiconductor devices at smaller andsmaller sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1J are cross-sectional views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIG. 2 is a cross-sectional view of a semiconductor device structure, inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Some embodiments of the disclosure are described. Additional operationscan be provided before, during, and/or after the stages described inthese embodiments. Some of the stages that are described can be replacedor eliminated for different embodiments. Additional features can beadded to the semiconductor device structure. Some of the featuresdescribed below can be replaced or eliminated for different embodiments.Although some embodiments are discussed with operations performed in aparticular order, these operations may be performed in another logicalorder.

FIGS. 1A-1J are cross-sectional views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments. In some embodiments, the semiconductor device structure tobe formed includes a resistive random access memory (RRAM) structure. Asshown in FIG. 1A, a semiconductor substrate 100 is received or provided.In some embodiments, the semiconductor substrate 100 is a bulksemiconductor substrate, such as a semiconductor wafer. For example, thesemiconductor substrate 100 includes silicon or other elementarysemiconductor materials such as germanium. In some other embodiments,the semiconductor substrate 100 includes a compound semiconductor. Thecompound semiconductor may include silicon carbide, gallium arsenide,indium arsenide, indium phosphide, another suitable compoundsemiconductor, or a combination thereof. In some embodiments, thesemiconductor substrate 100 includes a semiconductor-on-insulator (SOI)substrate. The SOI substrate may be fabricated using a separation byimplantation of oxygen (SIMOX) process, a wafer bonding process, anotherapplicable method, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in thesemiconductor substrate 100 to define and isolate various deviceelements (not shown) formed in the semiconductor substrate 100. Theisolation features include, for example, trench isolation (STI) featuresor local oxidation of silicon (LOCOS) features.

In some embodiments, various device elements are formed in and/or on thesemiconductor substrate 100. Examples of the various device elementsthat may be formed in the semiconductor substrate 100 includetransistors (e.g., metal oxide semiconductor field effect transistors(MOSFET), complementary metal oxide semiconductor (CMOS) transistors,bipolar junction transistors (BJT), high-voltage transistors,high-frequency transistors, p-channel and/or n-channel field effecttransistors (PFETs/NFETs), etc.), diodes, another suitable element, or acombination thereof. Various processes are performed to form the variousdevice elements, such as deposition, etching, implantation,photolithography, annealing, planarization, one or more other applicableprocesses, or a combination thereof.

In some embodiments, a dielectric layer 102 is formed over thesemiconductor substrate 100, as shown in FIG. 1A. The dielectric layer102 may include multiple sub-layers. The dielectric layer 102 may bemade of or include carbon-containing silicon oxide, silicon oxide,borosilicate glass (BSG), phosphoric silicate glass (PSG),borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG),porous dielectric material, another suitable low-k dielectric material,one or more other suitable materials, or a combination thereof.

In some embodiments, multiple conductive features are formed in thedielectric layer 102. The conductive features may include conductivecontacts, conductive lines, and/or conductive vias. The dielectric layer102 and the conductive features formed therein are a portion of aninterconnection structure that will be subsequently formed. Theformation of the dielectric layer 102 and the conductive features in thedielectric layer 102 may involve multiple deposition processes,patterning processes, and planarization processes. The device elementsin and/or on the semiconductor substrate 100 will be interconnectedthrough the interconnection structure to be formed over thesemiconductor substrate 100.

In some embodiments, a conductive feature 106 is formed in thedielectric layer 102, as shown in FIG. 1A. The conductive feature 106may be a conductive line. In some embodiments, a barrier layer 104 isformed between the conductive feature 106 and the dielectric layer 102.The barrier layer 104 may be used to prevent metal ions of theconductive features 104 from diffusing into the dielectric layer 102.

In some embodiments, trenches are formed in the dielectric layer 102.Each of the trenches may connect a via hole (not shown). The trenchesare used to contain conductive lines and the barrier layer. Theformation of the trenches may involve photolithography processes andetching processes. Afterwards, the barrier layer 104 is deposited overthe dielectric layer 102. The barrier layer 104 extends on sidewalls andbottom portions of the trenches. The barrier layer 104 may be made of orinclude tantalum nitride, titanium nitride, one or more other suitablematerials, or a combination thereof. The barrier layer 104 may bedeposited using a chemical vapor deposition (CVD) process, an atomiclayer deposition (ALD) process, a physical vapor deposition (PVD)process, an electroplating process, an electroless plating process, oneor more other applicable processes, or a combination thereof.

Afterwards, a conductive material layer is deposited over the barrierlayer 104 to fill the trenches, in accordance with some embodiments. Theconductive material layer may be made of or include copper, cobalt,tungsten, titanium, nickel, gold, platinum, graphene, one or more othersuitable materials, or a combination thereof. The conductive materiallayer may be deposited using a CVD process, an ALD process, a PVDprocess, an electroplating process, an electroless plating process, oneor more other applicable processes, or a combination thereof.

Afterwards, the barrier layer 104 and the conductive material layeroutside of the trenches are removed, in accordance with someembodiments. Remaining portions of the conductive material layer in oneof the trenches form the conductive feature 106. In some embodiments,the barrier layer 104 and the conductive material layer outside of thetrenches are removed using a planarization process. The planarizationprocess may include a CMP process, a dry polishing process, a mechanicalgrinding process, an etching process, one or more other applicableprocesses, or a combination thereof.

As shown in FIG. 1A, a dielectric layer 108 is deposited over thedielectric layer 102 and the conductive feature 106, in accordance withsome embodiments. The dielectric layer 108 may be made of or includesilicon carbide (SiC), nitrogen-doped silicon carbide, oxygen-dopedsilicon carbide, silicon nitride (SiN), silicon oxynitride (SiON),silicon oxide, one or more other suitable materials, or a combinationthereof. The dielectric layer 108 may be deposited using a CVD process,an ALD process, a PVD process, one or more other applicable processes,or a combination thereof. In some embodiments, the dielectric layer 108is patterned to form an opening 109 that exposes the conductive feature106, as shown in FIG. 1A.

As shown in FIG. 1B, a barrier layer 110 is deposited over thedielectric layer 108, in accordance with some embodiments. The barrierlayer 110 extends on the sidewalls and bottom portion of the opening109. The barrier layer 110 may be made of or include tantalum nitride,titanium nitride, one or more other suitable materials, or a combinationthereof. The barrier layer 110 may be deposited using a chemical vapordeposition (CVD) process, an atomic layer deposition (ALD) process, aphysical vapor deposition (PVD) process, an electroplating process, anelectroless plating process, one or more other applicable processes, ora combination thereof.

Afterwards, a conductive layer 112 is deposited over the barrier layer110, as shown in FIG. 1B in accordance with some embodiments. Theconductive layer 112 may fill the opening 109. The conductive layer 112is used as a lower electrode layer of a memory device that will beformed. The conductive layer 112 may be made of or include copper,cobalt, tungsten, titanium, nickel, gold, platinum, graphene, one ormore other suitable materials, or a combination thereof. The conductivelayer 112 may be deposited using a CVD process, an ALD process, a PVDprocess, an electroplating process, an electroless plating process, oneor more other applicable processes, or a combination thereof.

In some embodiments, the conductive layer 112 is planarized to providethe conductive layer 112 with a substantially planarized surface, whichmay facilitate subsequent formation processes. The conductive layer 112may be planarized using a chemical mechanical polishing (CMP) process, agrinding process, a dry polishing process, an etching process, one ormore other applicable processes, or a combination thereof.

As shown in FIG. 1C, a data storage layer 114 is deposited over theconductive layer 112, in accordance with some embodiments. The datastorage layer 114 is configured to store data unit. In some embodiments,the data storage layer 114 is a resistance variable layer which has avariable resistance representing the data unit. Depending upon thevoltage applied across the data storage layer 114, the variableresistance can be changed between different resistance statescorresponding to different data states of the data unit.

The data storage layer 114 may have reduced resistance after asufficiently high voltage is applied to the data storage layer 114. Theapplied voltage may induce ions (such as oxygen ions and/or nitrogenions) in the data storage layer 114 to move to the electrodes. As aresult, a series of vacancies are formed in the data storage layer 114.These vacancies may together form one or more conductive paths. Forexample, through a forming process, one or more conductive paths (forexample, conductive filaments) may be formed in the data storage layer114 so that the resistance of the data storage layer 114 is reducedsignificantly.

A reverse voltage may be applied to partially destroy the formedconductive filaments or the conductive paths. As a result, theresistance of the data storage layer 114 is increased. Therefore, theresistance of the data storage layer 114 may be adjusted through theapplication of voltage. The data may be stored in the data storage layer114. By detecting the current passing through the data storage layer114, information about the resistance of the data storage layer 114 isobtained. Therefore, the stored data is also obtained correspondingly.

In some embodiments, the data storage layer 114 is made of a dielectricmaterial and is usually electrically insulating. The data storage layer114 may be made of or include a metal oxide, a metal nitride, or acombination thereof. In some embodiments, the data storage layer 114 ismade of an oxygen-containing dielectric material. In some embodiments,the material of the data storage layer 114 includes hafnium oxide,aluminum oxide, tantalum oxide, zirconium oxide, hafnium aluminum oxide,one or more other suitable materials, or a combination thereof. In someembodiments, the data storage layer 114 has a thickness that is in arange from about 5 Å to about 100 Å.

Many methods may be used to form the data storage layer 114. In someembodiments, the data storage layer 114 is deposited using an ALDprocess, a CVD process, a PVD process, a spin-on process, a sprayingcoating process, one or more other applicable processes, or acombination thereof.

In some embodiments, the data storage layer 114 is in direct contactwith the conductive layer 112 which serves as a lower electrode layer.In some embodiments, due to the substantially planar surface provided bythe planarized conductive layer 112, adhesion between the data storagelayer 114 and the conductive layer 112 is improved.

Afterwards, an ion diffusion barrier layer 116 is deposited over thedata storage layer 114, as shown in FIG. 1C in accordance with someembodiments. In some embodiments, the ion diffusion barrier layer 116 isconfigured to prevent or slow material from diffusing from and/or intothe data storage layer 114. In some embodiments, the ion diffusionbarrier layer 116 is used to slow oxygen ions from diffusing from and/orinto the data storage layer 114. In some embodiments, the ion diffusionbarrier layer 116 is formed directly on the data storage layer 114. Inthese cases, the ion diffusion barrier layer 116 is in direct contactwith the data storage layer 114.

In some embodiments, the ion diffusion barrier layer 116 is made of ametal material doped with nitrogen, carbon, or a combination thereof.The metal material mentioned above may include titanium (Ti), tungsten(W), hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al),lanthanum (La), one or more other suitable or similar metal materials,or a combination thereof. For example, the ion diffusion barrier layer116 is made of or includes nitrogen-doped titanium, nitrogen-dopedtantalum, carbon-doped titanium, carbon-doped tantalum, one or moreother suitable metal materials doped with nitrogen and/or carbon, or acombination thereof.

In some embodiments, the ion diffusion barrier layer 116 is formed tohave an appropriate atomic concentration of nitrogen or carbon that isin a range from about 10% to about 45%. In some cases, if the atomicconcentration of nitrogen or carbon is smaller than about 10%, the iondiffusion barrier layer 116 may not have sufficient barrier ability. Insome other cases, if the atomic concentration of nitrogen or carbon isgreater than about 45%, the ion diffusion barrier layer 116 may havebarrier ability that is too strong. As a result, ions such as oxygenions may not be able to diffuse from and/or into the data storage layer114.

However, many variations and/or modifications may be made to embodimentsof the disclosure. The ion diffusion barrier layer 116 may have adifferent atomic concentration of nitrogen or carbon. In some otherembodiments, the ion diffusion barrier layer 116 is formed to have anatomic concentration of nitrogen or carbon that is in a range from about20% to about 35%.

In some embodiments, the ion diffusion barrier layer 116 is formed tohave an appropriate thickness that is in a range from about 5 Å to about70 Å. In some cases, if the thickness of the ion diffusion barrier layer116 is smaller than about 5 Å, the ion diffusion barrier layer 116 maynot have sufficient barrier ability. In some other cases, if thethickness of the ion diffusion barrier layer 116 is greater than about70 Å, the ion diffusion barrier layer 116 may have barrier ability thatis too strong. As a result, ions such as oxygen ions may not be able todiffuse from and/or into the data storage layer 114.

However, many variations and/or modifications may be made to embodimentsof the disclosure. The ion diffusion barrier layer 116 may have adifferent thickness. In some other embodiments, the ion diffusionbarrier layer 116 is formed to have a thickness that is in a range fromabout 15 Å to about 50 Å.

In some embodiments, the ion diffusion barrier layer 116 is depositedusing an ALD process, a CVD process, a PVD process, one or more otherapplicable processes, or a combination thereof. In some embodiments, thedeposition of the ion diffusion barrier layer 116 involves the usage ofa metal-containing gas and a dopant-containing gas. Thedopant-containing gas may be or include a nitrogen-containing gas, acarbon-containing gas, one or more other suitable gases, or acombination thereof.

Many variations and/or modifications can be made to embodiments of thedisclosure. In some other embodiments, a metal layer is deposited overthe data storage layer 114. Afterwards, an ion implantation process isused to dope the metal layer with nitrogen and/or carbon. As a result,the ion diffusion barrier layer 116 made of a metal material doped withnitrogen and/or carbon is formed.

As shown in FIG. 1C, a capping layer 118 is afterwards deposited overthe ion diffusion barrier layer 116, in accordance with someembodiments. In some embodiments, the capping layer 118 is used as anion reservoir region. The capping layer 118 may induce the formation ofvacancies in the data storage layer 114 during subsequent formingprocess and/or setting process. For example, the capping layer 118 isused to receive oxygen ions from the data storage layer 114. As aresult, vacancies forming the conductive paths or conductive filamentsare formed in the data storage layer 114. The forming and/or settingprocesses may therefore be achieved.

In some embodiments, the capping layer 118 is thicker than the iondiffusion barrier layer. In some embodiments, the capping layer 118 isformed to have an appropriate thickness that is in a range from about 10Å to about 150 Å. In some cases, if the thickness of the capping layer118 is smaller than about 10 Å, the capping layer 118 may not be able tocontain a sufficient amount of oxygen ions from the data storage layer114. As a result, the forming and/or setting processes may not be easyto perform. In some other cases, if the thickness of the capping layer118 is greater than about 150 Å, the operation speed for the resetprocess may be slowed down. In some embodiments, the ratio of thethickness of the ion diffusion barrier layer 116 to the thickness of thecapping layer 118 is in a range from about 0.02 to about 0.2.

In some embodiments, the capping layer 118 is made of a metal material.In some embodiments, the capping layer 118 is made of or includestitanium (Ti), hafnium (Hf), zirconium (Zr), lanthanum (La), tantalum(Ta), nickel (Ni), tungsten (W), one or more other suitable metalmaterials, or a combination thereof. In some embodiments, the cappinglayer 118 is made of a pure metal material or a combination of puremetal materials. In some embodiments, the capping layer 118 includessubstantially no nitrogen or carbon. In some embodiments, the cappinglayer 118 is deposited using a PVD process, a CVD process, an ALDprocess, a plating process, one or more other applicable processes, or acombination thereof.

Afterwards, a conductive layer 120 is deposited over the capping layer118, as shown in FIG. 1C in accordance with some embodiments. Theconductive layer 120 is used as an upper electrode layer of a memorydevice that will be formed. The conductive layer 120 may be made of orinclude copper, cobalt, tungsten, titanium, nickel, gold, platinum,graphene, one or more other suitable materials, or a combinationthereof. The conductive layer 120 may be deposited using a CVD process,an ALD process, a PVD process, an electroplating process, an electrolessplating process, one or more other applicable processes, or acombination thereof.

As shown in FIG. 1D, a mask element 122 is formed over the conductivelayer 120, in accordance with some embodiments. The mask element 122 isused to assist in subsequent patterning process of the conductive layer120, the capping layer 118, and the ion diffusion barrier layer 116. Themask element 122 may be made of or include silicon nitride, siliconoxynitride, silicon oxide, one or more other suitable materials, or acombination thereof. A photolithography process and an etching processmay be used to form the mask element 122.

Many variations and/or modifications can be made to embodiments of thedisclosure. In some other embodiments, the mask element 122 is notformed.

As shown in FIG. 1E, the conductive layer 120, the capping layer 118,and the ion diffusion barrier layer 116 are partially removed to bepatterned, in accordance with some embodiments. After the patterningprocesses, the data storage layer 114 is exposed. In some embodiments,the conductive layer 120, the capping layer 118, and the ion diffusionbarrier layer 116 are partially removed using one or more etchingprocesses. In some embodiments, the data storage layer 114 is partiallyremoved during the patterning of the conductive layer 120, the cappinglayer 118, and the ion diffusion barrier layer 116.

As shown in FIG. 1F, a protective layer 124 is deposited over thestructure shown in FIG. 1E, in accordance with some embodiments. Theprotective layer 124 may be made of or include silicon nitride, siliconoxynitride, silicon oxide, one or more other suitable materials, or acombination thereof. In some embodiments, the protective layer 124 isdeposited using a CVD process, an ALD process, a spin-on process, a PVDprocess, one or more other applicable processes, or a combinationthereof.

As shown in FIG. 1G, the protective layer 124 is partially removed toform a protective element 126, in accordance with some embodiments. Theprotective element 126 covers sidewalls of the conductive layer 120, thecapping layer 118, and the ion diffusion barrier layer 116. An etchingprocess may be used to form the protective element 126. During theetching process, the mask element 122 may also be etched. As a result, amask element 122′ with a smaller thickness may be formed.

Many variations and/or modifications can be made to embodiments of thedisclosure. In some other embodiments, the protective layer 124 or theprotective element 126 is not formed.

As shown in FIG. 1H, the data storage layer 114, the conductive layer112, and the barrier layer 110 are partially removed to be patterned, inaccordance with some embodiments. In some embodiments, the data storagelayer 114, the conductive layer 112, and the barrier layer 110 arepartially removed using one or more etching processes. The protectiveelement 126 and the mask element 122′ may together function as anetching mask during the patterning of the data storage layer 114, theconductive layer 112, and the barrier layer 110.

As shown in FIG. 1I, a protective layer 128 is deposited over thestructure shown in FIG. 1H, in accordance with some embodiments. In someembodiments, the protective layer 128 contains silicon, oxygen, and/orcarbon. The protective layer 128 may be made of or include siliconoxide, silicon nitride, silicon carbide, silicon oxynitride, one or moreother suitable materials, or a combination thereof. In some embodiments,the protective layer 128 is made of a material that is substantiallyfree of oxygen. In some embodiments, the protective layer 128 is asingle layer. In some other embodiments, the protective layer 128includes multiple sub-layers. The sub-layers may be made of the samematerial. Alternatively, some of the sub-layers are made of differentmaterials. The protective layer 128 may be deposited using a CVDprocess, an ALD process, a PVD process, a spin-on process, one or moreother applicable processes, or a combination thereof.

Afterwards, a dielectric layer 130 is deposited over the protectivelayer 128, as shown in FIG. 1I in accordance with some embodiments. Thedielectric layer 130 may be made of or include carbon-containing siliconoxide, silicon oxide, borosilicate glass (BSG), phosphoric silicateglass (PSG), borophosphosilicate glass (BPSG), fluorinated silicateglass (FSG), porous dielectric material, another suitable low-kdielectric material, one or more other suitable materials, or acombination thereof. The dielectric layer 130 may be deposited using aCVD process, an ALD process, a PVD process, a spin-on process, a spraycoating process, one or more other applicable processes, or acombination thereof.

As shown in FIG. 1J, a conductive feature 134 is formed in thedielectric layer 130, in accordance with some embodiments. Theconductive feature 134 is electrically connected to the conductive layer120. In some embodiments, the conductive feature 134 is a conductivevia. In some embodiments, the conductive feature 134 is a conductiveline. In some embodiments, the conductive feature 134 is a combinationof a conductive via and a conductive line which is formed using a dualdamascene process.

In some embodiments, a barrier layer 132 is formed before the formationof the conductive feature 134. The material and formation method of thebarrier layer 132 may be the same as or similar to those of the barrierlayer 104. The material and formation method of the conductive feature134 may be the same as or similar to those of the conductive feature106.

As shown in FIG. 1J, a semiconductor device with a resistive randomaccess memory (RRAM) structure is formed, in accordance with someembodiments. The conductive layers 112 and 120 serve as a lowerelectrode and an upper electrode, respectively. The conductive layers112 and 120 sandwich the data storage layer 114, the ion diffusionbarrier layer 116, and the capping layer 118. The RRAM structure employsoxygen vacancies to manipulate the resistance of the data storage layer114. When a set voltage is applied across the conductive layers 112 and120, ions such as oxygen ions in the data storage layer 114 move throughthe ion diffusion barrier layer 116 to the capping layer 118, therebyre-forming conductive paths (initially formed by a form voltage) fromoxygen vacancies and switching the variable resistance to the lowresistance state. The set voltage is, for example, a positive voltage.When a reset voltage is applied across the conductive layers 120 and112, the ions such as oxygen ions move back to the data storage layer114 through the ion diffusion barrier layer 116, thereby filling theoxygen vacancies and switching the variable resistance to the highresistance state. The reset voltage is, for example, a negative voltage.

Ion diffusion is a challenge for RRAM structure at high operatingtemperatures or under repeated operations. For example, under the highresistance state, the oxygen ions may slowly diffuse back to the cappinglayer 116 due to concentration gradient. As a result, the conductivefilaments or the conductive paths may be formed again, which decreasesresistance of the data storage layer 114. Alternatively, under the lowresistance state, the oxygen ions may slowly diffuse back to the datastorage layer 114. As a result, the conductive filaments or theconductive paths may be partially destroyed, which increases resistanceof the data storage layer 114. As the diffusion occurs, the variableresistance either increases or decreases eventually toggling the stateof the variable resistance between the high and low resistivity states.This undesirably changes the state of the data unit represented by thevariable resistance, thereby resulting in data corruption and reduceddata retention.

In some embodiments, because of the ion diffusion barrier layer 116formed between the data storage layer 114 and the capping layer 118, theundesired ion diffusion is prevented or slowed down. For example, underthe high resistance state, the oxygen ions are prevented from diffusingback to the capping layer 118 from the data storage layer 114 due to theion diffusion barrier layer 116. Therefore, there is substantially noundesired conductive filament formed in the data storage layer 114. Thedata storage layer 114 may still be under the high resistance state. Forexample, under the low resistance state, the oxygen ions are preventedfrom diffusing back to the data storage layer 114 from the capping layer118 due to the ion diffusion barrier layer 116. Therefore, theconductive filaments in the data storage layer 114 are prevented frombeing damaged since oxygen ions are blocked. The data storage layer 114may still be under the low resistance state. The performance, retention,and reliability of the RRAM structure are improved. In some embodiments,the switching window is improved by about 1.5 times to about 2.5 times,when compared with other embodiments without the ion diffusion barrierlayer 116.

Many variations and/or modifications can be made to embodiments of thedisclosure. FIG. 2 is a cross-sectional view of a semiconductor devicestructure, in accordance with some embodiments. In some embodiments, astructure the same as or similar to that shown in FIG. 1A is provided orreceived. In some embodiments, before the lower electrode layer (such asthe conductive layer 112) is formed, the dielectric layer 108 is formedover the semiconductor substrate 100. Afterwards, the opening 109 isformed in the dielectric layer 108. In some embodiments, the barrierlayer 110 and the conductive layer 112 are formed. Portions of thebarrier layer 110 and the conductive layer 112 extends into the opening109. In some embodiments, the conductive layer 112 is not planarized.Therefore, the conductive layer 112 includes a curved upper surface. Insome embodiments, the subsequently formed layers 114, 116, 118, and 120also include curved upper surfaces accordingly, as shown in FIG. 2 .

Embodiments of the disclosure form a semiconductor device including aresistive random access memory (RRAM) structure. The RRAM structureincludes a data storage layer and a capping layer which are sandwichedbetween a lower electrode and an upper electrode. An ion diffusionbarrier layer made of a metal material doped with nitrogen and/or carbonis formed between the data storage layer and the capping layer. The iondiffusion barrier layer may be used to prevent undesired ion diffusionbetween the data storage layer and the capping layer. Therefore, thequality and reliability of the semiconductor device structure aresignificantly improved.

In accordance with some embodiments, a method for forming asemiconductor device structure is provided. The method includes forminga lower electrode layer over a semiconductor substrate and forming adata storage layer over the lower electrode layer. The method alsoincludes forming an ion diffusion barrier layer over the data storagelayer and forming a capping layer over the ion diffusion barrier layer.The ion diffusion barrier layer is a metal material doped with nitrogen,carbon, or a combination thereof. The capping layer is made of a metalmaterial. The method further includes forming an upper electrode layerover the capping layer.

In accordance with some embodiments, a method for forming asemiconductor device structure is provided. The method includes forminga lower electrode layer over a semiconductor substrate and forming aresistance variable layer over the lower electrode layer. The methodalso includes forming a barrier layer over the resistance variable layerand forming a capping layer over the barrier layer. The capping layer ismade of a metal material, and the capping layer is in direct contactwith the barrier layer. The method further includes forming an upperelectrode layer over the capping layer.

In accordance with some embodiments, a semiconductor device structure isprovided. The semiconductor device structure includes a semiconductorsubstrate and a lower electrode over the semiconductor substrate. Thesemiconductor device structure also includes a resistance variable layerover the lower electrode and an ion diffusion barrier layer over theresistance variable layer. The ion diffusion barrier layer is a metalmaterial doped with nitrogen or carbon. The semiconductor devicestructure further includes a capping layer over the ion diffusionbarrier layer, and the capping layer is made of a metal material. Inaddition, the semiconductor device structure includes an upper electrodeover the capping layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device structure, comprising: asemiconductor substrate; a data storage element over the semiconductorsubstrate; an ion diffusion barrier element over the data storageelement; a protective element extending along a sidewall of the iondiffusion barrier element, wherein a bottom surface of the protectiveelement is between a top surface of the data storage element and abottom surface of the data storage element; a first electrodeelectrically connected to the data storage element; and a secondelectrode electrically connected to the data storage element.
 2. Thesemiconductor device structure as claimed in claim 1, wherein the datastorage element is made of an oxygen-containing dielectric material. 3.The semiconductor device structure as claimed in claim 1, wherein theion diffusion barrier element is a metal material doped with nitrogen.4. The semiconductor device structure as claimed in claim 1, wherein theion diffusion barrier layer is a metal material doped with carbon. 5.The semiconductor device structure as claimed in claim 1, wherein alower portion of the data storage element is wider than an upper portionof the data storage element.
 6. The semiconductor device structure asclaimed in claim 1, wherein the protective element has an inner edge andan outer edge, the inner edge is between the outer edge and the datastorage element, and the outer edge is substantially aligned with anedge of the first electrode.
 7. The semiconductor device structure asclaimed in claim 1, wherein the data storage element is in directcontact with the ion diffusion barrier element.
 8. The semiconductordevice structure as claimed in claim 1, further comprising a cappingelement, wherein the ion diffusion barrier element is between thecapping element and the data storage element.
 9. The semiconductordevice structure as claimed in claim 8, wherein the capping elementcomprises titanium, hafnium, zirconium, tantalum, nickel, or tungsten.10. The semiconductor device structure as claimed in claim 1, whereinthe data storage element is wider than the ion diffusion barrierelement.
 11. A semiconductor device structure, comprising: asemiconductor substrate; a data storage element over the semiconductorsubstrate, wherein a lower portion of the data storage element is widerthan an upper portion of the data storage element, the data storageelement has a surface connecting a first sidewall of the lower portionand a second sidewall of the upper portion, and slopes of the surfaceand the first sidewall are different from each other; an ion diffusionbarrier element over the data storage element; a first electrodeelectrically connected to the data storage element; and a secondelectrode electrically connected to the data storage element.
 12. Thesemiconductor device structure as claimed in claim 11, wherein the lowerportion of the data storage element has a lower sidewall, and the lowersidewall is substantially aligned with an edge of the first electrode.13. The semiconductor device structure as claimed in claim 11, whereinthe upper portion of the data storage element has an upper sidewall, andthe upper sidewall is substantially aligned with an edge of the iondiffusion barrier element.
 14. The semiconductor device structure asclaimed in claim 13, further comprising a protective element extendingalong the upper sidewall of the upper portion of the data storageelement.
 15. The semiconductor device structure as claimed in claim 14,wherein a bottom surface of the protective element is between a topsurface of the data storage layer and a bottom surface of the datastorage layer.
 16. A semiconductor device structure, comprising: asemiconductor substrate; a lower electrode over the semiconductorsubstrate; a resistance variable element over the lower electrode; anupper electrode over the resistance variable element; and a protectiveelement extending along a sidewall of the resistance variable element,wherein the protective element has an inner edge and an outer edge, theinner edge is between the outer edge and the resistance variableelement, and the outer edge is substantially aligned with an edge of thelower electrode.
 17. The semiconductor device structure as claimed inclaim 16, wherein the protective element gradually shrinks along adirection from a bottom of the protective element towards a top of theprotective element.
 18. The semiconductor device structure as claimed inclaim 16, wherein the protective element is in direct contact with theresistance variable element.
 19. The semiconductor device structure asclaimed in claim 16, wherein the protective element is in direct contactwith a sidewall of the upper electrode.
 20. The semiconductor devicestructure as claimed in claim 16, wherein a bottom surface of theprotective element is between a top surface of the resistance variableelement and a bottom surface of the resistance variable element.